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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
Features
* Integrated 2.488Gb/s Transceiver * SONET/SDH Transport Overhead Output * SONET/SDH Transport Overhead Modification * B1 Error Detection, Re-calculation, and Insertion
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
* Support for Multiple SONET/SDH Rates * LOF/SEF Alarm Generation * Section & Line AIS Insertion * 50 Source Terminated 2.488Gb/s I/O
General Description
The VSC8151 is a 2.488Gb/s Section Termination device which both monitors and modifies the section and line overhead of a received SONET/SDH signal, and can generate AIS-L maintenance signals for trouble sectionalization. These features allow all section termination requirements to be supported for Operations, Administration, Management, and Provisioning (OAM&P) functions in SONET/SDH terminal and optical networking applications. An integrated 2.488Gb/s serial transceiver isolates the SONET/SDH signal interface, allowing protocol information to be exchanged with programmable logic using a low-speed TTL interface.
VSC8151 Functional Block Diagram
LOS CONTROL & ALARM DETECTION RXFRERR RXSEF RXLOF
RXSIN+/RXSCLKIN+/POUTCLK RXPIN[15:0] SYSRST TXSCLKIN+/TXOHWI TXWRENA TXADDR[5:0] TXOHIN[7:0] TXFPOUT
1:8 DMX
RXPIN[7:0]
FRAMING
DESCRAMBLER
OVERHEAD OUTPUT
RXFPOUT RXOHCLK RXOHOUT[7:0]
B1 MONITOR TXPOUT[15:0] ASSEMBLER OVERHEAD INPUT & INTERNAL CONTROL POUTCLK
AIS GENERATION
SCRAMBLER & B1 CALC
8:1 MUX
TXSCLKOUT+/TXSOUT+/-
NOTE: References (R#-#) or (O#-#) refer to the SONET requirement or option specification listed in Bellcore document GR-253 CORE Issue 2, Rev. 2, January 1999.
Functional Overview
The VSC8151 is divided into two logic sections, a monitoring section and a modification section, each interfaced externally through both 2.5Gb/s serial interfaces as well as 16-bit parallel interfaces. Incoming
G52225-0, Rev. 2.9 12/1/99
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Page 1
VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Advance Product Information
VSC8151
SONET/SDH data is demultiplexed, framed, descrambled, and the 27 bytes of the section and line overhead are output. The BIP parity of the incoming signal is calculated and compared with the received B1 and B2 bytes for calculating received parity errors. The byte aligned data, calculated B1/B2 parity, and frame boundary location are then passed to the modification section where new overhead bytes are inserted. The modified data is rescrambled, and B1/B2 parity recalculated (if desired) prior to serialization and output. An internal state machine generates a section alarm inhibit signal (AIS) with user defined transport overhead that can be alternatively transmitted in place of the received signal.
2.5G Serial and Parallel Input Interfaces
The demux receives differential clock and data signals at the appropriate SONET/SDH rate and demultiplexes the data for framing. These inputs are internally terminated by a center-tapped resistor network and include biasing resistors to facilitate AC coupling. For differential input DC coupling, the network is terminated to the appropriate termination voltage VTerm providing a 50 to VTerm termination for both true and complement inputs. For differential input AC coupling, the network is terminated to V Term via a blocking capacitor. The common mode reference voltage is created by a resistor divider as shown. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DC-coupling operations, it is recommended that the user provides an external reference voltage which has better temperature and power supply noise rejection than the on-chip resistor divider. The external reference should have a nominal value equivalent to the common mode switch point of the DC coupled signal, and can be connected to either side of the differential gate. Figure 1: High Speed Serial Clock and Data Inputs
Chip Boundary VCC
= 3.3V
ZO
CIN
1.65V 50
1.65V
CAC R | | = 1.5k VTERM CSE ZO VEE = 0V 50
CIN TYP = 100 pF (clock), 100nF (data) CSE TYP = 100 pF (clock), 100nF (data) for single ended applications.
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52225-0, Rev. 2.9 12/1/99
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
The serial demux can be bypassed and the 16-bit single-ended PECL bus RXPIN[15:0] can be used to input SONET/SDH data for applications where the data has already been deserialized by a previous device. This mode is selected by asserting the EQULOOP input (active high). Input setup and hold requirements are specified with respect to the falling edge of POUTCLK; the user is responsible for meeting loop timing requirements between the VSC8151 and previous device. The user must still provide a line rate clock to the serial clock input RXSLKIN+/- to provide a high-speed output clock to the mux and the means to create the divide-by-16 POUTCLK.
2.5G Serial and Parallel Output Interfaces
The high speed clock and data output driver consists of a differential pair designed to drive a 50 transmission line. The transmission line should be terminated with a 100 resistor at the load between true and complement outputs. No connection to a termination voltage is required. The output driver is source terminated to 50 on-chip, providing a snubbing of any reflections. If used single-ended, one way to terminate the output driver is differentially at the load with a 100 resistor between true and complement outputs. See Figure 2A. Another option is to terminate the used output at the load with 50 ohm to VTERM and the unused output with 50 ohm to VTERM at the source. See Figure 2B. In some applications, it may be desirable to turn off the high speed outputs (TXSOUT, TXSCLKOUT) to reduce power. To disable the high speed clock output, tie pin 22 to VCC (3.3V) instead of GND. To disable the high speed data output, tie pin 17 to VCC (3.3V) instead of GND. Turning off each output will reduce maximum current consumption by 107mA for the clock output, and 122mA for the data output.
Figure 2: High Speed Output Driver & Termination
Figure 2A
VCC
50
50 100
Pre-Driver
Z0 = 50
Figure 2B
VCC
VTERM 50
VEE
50
50
Pre-Driver
50 VTERM
Z0 = 50
VEE
G52225-0, Rev. 2.9 12/1/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
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VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Advance Product Information
VSC8151
The serial mux output can be bypassed and the 16-bit single-ended PECL bus TXPOUT[15:0] can be used to output modified SONET/SDH data or AIS to another device. These outputs are enabled by setting the DP bit in the MISC register appropriately, and should be disabled if not being used. It is possible to use both the 16-bit parallel output bus and the 2.5Gb/s serial output simultaneously. The POUTCLK output is used to provide a bus output clock for RXFPOUT and is a divide-by-16 version of TXSCLKIN.
2.5G Output Clocking Domains
The 2.5GHz clock input to the VSC8151 mux (TXSCLKIN) acts as the permanent transmit clock for the VSC8151. An internal clock domain boundary exists between the monitor and the transmit sections of the device, allowing the AIS transmit portion to function completely independently of the receive portion. This allows a CDR to track whatever data is being received and allows the VSC8151 to monitor in-frame status of the signal continuously. During a LOS condition, the CDR clock output may drift outside of the SONET/SDH transmission standard of +/-20PPM. By providing the option of using an external clock multiplication unit (CMU), one can maintain a standard of +/-20PPM even during AIS states. This backup CMU receives it's timing reference from either a local AIS reference or the divided clock from the received RXSCLKIN +/-, depending whether AIS transmit mode is selected or not. The user controls the source of the reference clock output through settings in the VSC8151 register file. The user will change these settings at the same time AIS is asserted or when imminent loss of RXSCLKIN clock quality exists. The AIS reference output can be switched from a divided down RXSCLKIN signal to a copy of one of the external references, ensuring that a proper reference clock remains for the transmit multiplexer. (See Table 2: VSC8151 Configuration Registers, Definition 13)
Figure 3: VSC8151 using CMU as Transmit Timing Source
RXSIN+/2.488Gb/s Data 622Mb/s Data 155MB/s Data SEF/LOF ALARMS
Received Data
Clock and Data Recovery
VSC8122
2.488GHz Clock 622MHz Clock 155MHz Clock RXSCLKIN+/-
Demux & Monitor Logic
AIS State Machine
AIS Insert
Clock Multiplication Unit
VSC812X
TXSCLKIN+/2.488GHz Clock 622MHz Clock 155MHz Clock
Modify Logic
CMU Reference Generator
Mux & Frame Assembly Logic
TXSOUT+/TXSCLKOUT+/-
AIS Reference 78 MHz
AIS Reference 155/78 MHz
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52225-0, Rev. 2.9 12/1/99
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
If the user chooses to use the CDR as a timing source even during AIS mode, the output of the CDR can be connected single ended to both RXSCLKIN and TXSCLKIN, or a multi-drop connection can be made differentially. Figure 4: VSC8151 using CDR as Transmit Timing Source
RXSIN+/2.488Gb/s Data 622Mb/s Data 155MB/s Data SEF/LOF ALARMS
Received Data
Clock and Data Recovery
VSC8122
2.488GHz Clock 622MHz Clock 155MHz Clock RXSCLKIN+/-
Demux & Monitor Logic
AIS State Machine
AIS Insert
TXSCLKIN+/2.488GHz Clock 622MHz Clock 155MHz Clock
Modify Logic
CMU Reference Generator
Mux & Frame Assembly Logic
TXSOUT+/TXSCLKOUT+/-
AIS Reference 78 MHz
AIS Reference 155/78 MHz
SONET/SDH Monitoring Circuitry Overview
The monitoring circuitry provides SONET/SDH compliant framing and framing alarms, as well as detecting B1 and B2 parity errors and transport overhead byte output.
Framing The frame acquisition algorithm determines the in-frame/out-of-frame status of the receiver. Out-of-frame is defined as a state where the frame boundaries of the received SONET/SDH signal are unknown, i.e. after system reset or if for some reason the receiver looses synchronization, e.g. due to `bit slips'. In-frame is defined as a state where the frame boundaries are known. The receiver monitors the frame synchronization by checking for the presence of a portion of the A1/A2 framing pattern every 125uS. If one or more bit errors are detected in the expected A1/A2 framing pattern output RXFRERR (active high) will be asserted (See Figure 5). If framing pattern errors are detected for four consecutive frames a Severely Errored Frame (SEF) alarm will be asserted on output RXSEF (active high) (R5223).
G52225-0, Rev. 2.9 12/1/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
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VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Advance Product Information
VSC8151
Figure 5: Functional Block Diagram of Frame Acquisition Circuit
FRD SL1 SL0 RXFRERR RXSEF RXLOF RXFPOUT FRAME SYNC. COUNTER RESYNC BYTE ALIGN Aligned Output
ERROR/ALARM DETECTION
RXSIN
1:8 DMX
FRAME DET
The frame boundary detection/verification is based on 12, 24 or 48 bits of the A1/A2 overhead (See Figure 6) depending on the setting of the FRDET register (See Table 2). Frame acquisition procedures are controlled by the settings of the FRDET register. Reframing can be controlled manually or reframing can automatically be initiated by the presence of an SEF signal. Using SEF as an indicator that reframe is necessary will achieve realignment within 250uS or the receipt of two error free framing patterns (R5-225) A frame detect based on 24 bits will result in an SEF alarm at an average of no more than once every 6 minutes assuming a BER of 10-3 (R5-224). A frame detect based on 48 bits or 12 bits will result in a mean time between SEF detects of 0.43 minutes and 103 minutes respectively. Figure 6: Frame Detection Patterns
48 bits 24 bits 12 bits
A1 (0xF6)
A1 (0xF6)
A1 (0xF6)
A2 (0x28)
A2 (0x28)
A2 (0x28)
Loss of Signal The LOS (Loss of Signal, active high) input should be asserted whenever the interfacing module no longer generates a valid electrical signal on the high speed clock and/or data lines of the VSC8151. If the clock signal is present when the LOS input is asserted the VSC8151 will assert SEF and other outputs will become invalid. If the input clock is not present, then the transition of the LOS input will not be detected and the part is effectively frozen. Asserting LOS will force SEF (Severely Errored Frame) and LOF (Loss of Frame) high, and force all 0's to be output from the device, regardless of the input.
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52225-0, Rev. 2.9 12/1/99
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Loss of Frame A Loss of Frame (LOF) defect is declared (RXLOF active high) when a Severely Errored Frame (SEF) condition persists for 3ms (R6-59). The LOF state detection is based on an integrating timer to prevent sporadic errors from asserting LOF, such as a periodic 1ms error. An LOF defect is cancelled after an in-frame condition (SEF low) persists for 3ms (R6-61) because an integrating timer approach has been implemented (O6-62). Multiple SONET/SDH Rate Functionality The VSC8151 supports three SONET/SDH rates: STS-48/STM-16, STS-12/STM-4, and STS-3/STM-1. The user is responsible for rate-provisioning the device by setting the RATESEL register (See Table 2). The device requires clocks RXSCLKIN+/- and TXSCLKIN+/- to match the selected data rate in order for internal circuitry to function correctly. The RATESEL register changes the expected frame length of the received signal and selects the characteristics of the outgoing traffic or AIS signal. LOF integration timing remains 3ms regardless of selected SONET/SDH rate. Descrambler Framed SONET/SDH bytes are descrambled using a frame synchronous descrambler with generating polynomial 1 + X6 + X7 and a sequence length of 127. The scrambling algorithm is reset to an all 1's state immediately following the Z0 byte (last channel of first row, third column). The A1, A2, and J0/Z0 bytes are not descrambled (R5-6). The descrambler can be disabled by setting the MISC register appropriately. B1 Error Monitoring The bit-interleaved parity (BIP-8) error detection code (B1) will be calculated for every received frame before descrambling and compared to the descrambled B1 value in the following frame (R3-16). The results of this calculation are used to generate a B1 parity mask that is output using the overhead output interface. The calculated B1 parity used to do this comparison can be substituted in the received data stream and output. This effectively `corrects' the B1 byte and prevents the same B1 errors from being detected downstream. B2 Error Monitoring Incoming B2 errors for the first STS-1 are monitored and detected. This circuitry is not designed to supply B2 error rate monitoring but exists to provide support for modification of the overhead bytes of the line overhead. Incoming B2 parity must be determined because modification of the line overhead requires that the B2 byte for the first STS-1 be re-calculated. If the line overhead is not being modified by the user then the B2 error monitoring still takes place and the B2 errormask is output. Overhead Output The 9 bytes of the SONET section overhead and the 18 bytes in the first channel of the line overhead (See Figure 7) are made available to the user through the overhead output interface RXOHOUT[7:0], RXOHCLK, and RXFPOUT. Two additional bytes containing the results of the B1 and B2 parity error detection are also output. These 29 bytes are output from the RXOHOUT port, each accompanied by a pulse of RXOHCLK. The 27 overhead bytes are output in the order they are received, with a pulse on RXFPOUT appearing after the J0 byte. RXFPOUT is used to provide a reference point for the 29 byte output sequence of overhead bytes and clocks
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VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Advance Product Information
VSC8151
(See Figure 7). It is suggested that RXOHCLK be used to clock an external counter with RXFPOUT providing a counter reset. This allows the counter value to be correlated to a specific output byte and to be used as a write address for a register file. Figure 7: Functional Overhead Output Timing
= delay
RXOHOUT[7:0]
S1
M0
E2
A1
A2
J0
B1
E1
F1
B1MASK
RXOHCLK
RXFPOUT
The additional two bytes are parity error masks that indicate the number of received B1 and B2 errors. These bytes contain a parity error-mask of the results of the BIP calculation. Incoming parity errors are designated by a `1' in the corresponding bit position. A B1 or B2 error mask byte of 00H indicates no received parity errors for that frame, and a byte of 13H would indicate 3 of 8 bits were errored. The B1 error mask appears immediately after the F1 user byte is output and the B2 error mask appears immediately after the K2 APS byte is output. The RXOHOUT[7:0] output is undefined when SEF is high. RXFPOUT and RXOHCLK are functions of the received data being properly framed and will also be indeterminate during a SEF or LOS condition.
SONET/SDH Modification Circuitry Overview
The modification circuitry receives frame aligned data from the monitoring circuitry or from an internal state machine that generates a section AIS signal. The transport overhead of either signal can be modified by the user, including the insertion of recalculated B1 parity. These features encompass the requirements for performing section termination, as well as allowing the modification of line overhead bytes such as K1/K2 and the line DCC bytes.
Overhead Write Interface The 9 bytes of the section overhead and the 18 bytes of the first channel of the line overhead can be replaced with user defined bytes or allowed to pass through the part unchanged. The overhead write interface makes use of an internal 32 byte register file for storing the 27 overhead modifier bytes as well as providing internal configuration registers. TXWRENA, TXADDR[5:0], TXOHWI, and TXOHIN[7:0] are the write interface inputs.
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52225-0, Rev. 2.9 12/1/99
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Data present on the TXOHIN[7:0] bus is written to the internal register addressed by TXADDR[5:0] on the rising edge of TXWRENA. Assertion of TXOHWI (active high) during the overhead byte write cycle inhibits the modification of the addressed overhead byte.
A1/A2 Boundary Modification Only the first A1 and A2 bytes of the SONET/SDH can be modified. The A1 byte can be replaced with user defined data without affecting the framing algorithms of subsequent VSC8151 devices. An F6H byte can be resubstituted before exiting the subsequent VSC8151, effectively creating an in-band 64kb/s messaging channel. The A2 byte could be replaced by the user to intentionally corrupt the A1/A2 boundary and output a data stream that causes downstream network equipment to lose frame lock and enter alarm states. BIP-8 Recalculation & Modification The TXOHIN[7:0] information written to the B1 and B2 address location does not replace the outgoing BIP byte. The 8 bits form an XOR mask that will intentionally induce BIP errors into the outgoing data stream. A TXOHIN[7:0] word such as B2H would corrupt the BIP byte at bits 1, 4, 5, 7, and a downstream device will observe four parity errors. A TXOHIN[7:0] word of 00H will induce no parity errors, but will replace the BIP byte with a recalculated value. Setting the TXOHWI bit at the B1 or B2 location will prevent the BIP byte from being modified or corrected. Note that if there is any modification to the transport overhead it is necessary for the B1 byte to be corrected in order to prevent downstream parity errors. The B2 byte needs to be corrected if any changes are made to the line overhead for the same reason. Errors can be intentionally induced to the B2 channel to compensate for the lack of complete B2 error monitoring. Modifying the line overhead requires that the B2 byte in the first STS-1 be corrected, but this has the effect of artificially lowering the observed B2 error rate at subsequent line termination equipment (LTE). Correcting the B2 byte in the first STS-1 position will result in a 1/48th, 1/12th, or 1/3rd reduction depending on the provisioned SONET/SDH rate. Monitoring received B2 errors on the RXOHOUT[7:0] B2 errormask and rewriting this errormask to the B2 address will keep the outgoing B2 error rate consistent with the received B2 error rate. Alarm Indication Signal (AIS) Overhead Modification Transport overhead modification procedures are identical for AIS transmission mode. TXFPOUT is sourced from the frame counters resident within the receive framing circuitry during non-AIS transmission mode. During an AIS condition valid SONET/SDH data is no longer being received, resulting in the part entering a LOF or LOS state. Counters in the receive framing block will be invalid during this time, therefore when AIS is asserted the TXFPOUT signal is sourced from a redundant set of frame counters present within the AIS generation state machine. The frame counters for AIS block are separate from the receive framing circuitry, and as a result the TXFPOUT signal will be in an unknown state during a AIS mode transition, but will become periodic again after 125us. User logic should anticipate a late or early TXFPOUT pulse when switching in and out of AIS mode.
G52225-0, Rev. 2.9 12/1/99
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VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Advance Product Information
VSC8151
Line Overhead Modification It is understood that the ability to modify a portion of the line overhead is not permitted in a section termination function. The ability to do so has been included in order to leave such decisions at the users discretion. Scrambler The outgoing data bytes are scrambled with a generating polynomial of 1 + X6 + X7 and sequence length of 127, prior to being multiplexed and output as a serial signal. The A1, A2, and J0/Z0 bytes are not scrambled. The scrambler can be disabled by setting a bit in the MISC configuration register. A1/A2 Boundary Refresh The FWAx control in the register file forces the 8151 to re-write the entire A1/A2 boundary and to refresh the F6H and 28H bytes while in frame. This feature allows the device to continue to output a valid A1/A2 boundary if input data suddenly disappears, and AIS has not been initiated. In the event that the incoming data disappears, a valid A1/A2 will still appear in the historical frame boundary location, allowing downstream devices to remain in frame until AIS can be initiated. AIS Generation The VSC8151 can be configured to output a section level AIS stream in lieu of passing SONET/SDH data received from the RXSIN and RXSCLKIN inputs. This is typically done during LOS or LOF conditions to relay information about the failure by utilizing the section DCC bytes and keep the downstream sections in-frame and monitored while fault isolation to takes place. Setting the AISMODE configuration register replaces the received data stream with an internally generated AIS-L signal appropriate for section terminating equipment. This signal contains user-defined section overhead and an all-1's pattern for the remainder of the bytes (R6-163), conveniently generating AIS for all higher SONET/SDH alarm levels. The section and line overhead bytes can be modified during AIS in the same manner that they may in a non-AIS mode. During the AIS state, the relative A1/A2 boundary can be preserved so that downstream devices will not be forced to reframe on a new signal. By using the A1/A2 bounder refresh (previous paragraph), the user can initiate a seamless AIS transition without forcing downstream nodes to enter SEF and frame search state. Initialization & Configuration Upon power up of the VSC8151, the user should apply a positive pulse to the system reset pin (SYSRST) for at least 32 high speed (2.4GHz) clock cycles (12.8ns). Pulsing SYSRST resets all the counters, synchronizers and state machines used by the 8151. The device must also be configured upon startup by properly setting the TEST, RATE_SEL, FRMDET, AIS_MODE, and MISC registers (See Table 2) using the overhead write interface. TEST must be initialized to an 00H pattern for proper operation. The TXOHWI bit should be set appropriately for all 27 overhead modification registers. No default state exists for all configuration and overhead registers, they must be initialized upon startup. The PT bit of the MISC register has the effect of making the VSC8151 non-intrusive and function as if in a monitor only mode by internally asserting all TXOHWI bits.
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VSC8151
Table 1: VSC8151 Register File Mapping Register Name
OHS0 OHS1 OHS2 OHS3 OHS4 OHS5 OHS6 OHS7 OHS8 OHL0 OHL1 OHL2 OHL3 OHL4 OHL5 OHL6 OHL7 OHL8 OHL9 OHL10 OHL11 OHL12 OHL13 OHL14 OHL15 OHL16 OHL17
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Address TXOHA[4:0]
5'h00 5'h01 5'h02 5'h03 5'h04 5'h05 5'h06 5'h07 5'h08 5'h09 5'h0A 5'h0B 5'h0C 5'h0D 5'h0E 5'h0F 5'h10 5'h11 5'h12 5'h13 5'h14 5'h15 5'h16 5'h17 5'h18 5'h19 5'h1A
Data & Overhead Write Inhibit TXOHD[7:0], OHWI
SONET #1 STS-1 A1 Modifier SONET #1 STS-1 A2 Modifier SONET #1 STS-1 J0 Modifier B1 Error Mask SONET #1 STS-1 E1 Modifier SONET #1 STS-1 F1 Modifier SONET #1 STS-1 D1 Modifier SONET #1 STS-1 D2 Modifier SONET #1 STS-1 D3 Modifier SONET #1 STS-1 H1 Modifier SONET #1 STS-1 H2 Modifier SONET #1 STS-1 H3 Modifier B2 Error Mask SONET #1 STS-1 K1 Modifier SONET #1 STS-1 K2 Modifier SONET #1 STS-1 D4 Modifier SONET #1 STS-1 D5 Modifier SONET #1 STS-1 D6 Modifier SONET #1 STS-1 D7 Modifier SONET #1 STS-1 D8 Modifier SONET #1 STS-1 D9 Modifier SONET #1 STS-1 D10 Modifier SONET #1 STS-1 D11 Modifier SONET #1 STS-1 D12 Modifier SONET #1 STS-1 S1 Modifier SONET #1 STS-1 M0/1 Modifier SONET #1 STS-1 E2 Modifier
Table 2: VSC8151 Configuration Registers Register Name
TEST RATE_SEL FRMDET AIS_MODE MISC
Address TXOHA[4:0]
5'h1B 5'h1C 5'h1D 5'h1E 5'h1F
7
0 X X X X
6
0 X X X X
Data ( TXOHD[7:0] ) 5 4 3 2
0 X X X X 0 X X X X 0 FWAx 0 NS
1
0 OC12 SL1 PT
0
0 OC3 SL0 AIS DP
FRD1 FRD0 DS DD
MXC1 MXC0 B2G
Note: TEST register must be initialized to 00H
G52225-0, Rev. 2.9 12/1/99
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2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Advance Product Information
VSC8151
Configuration Register Definitions 1. OC12 | OC3 Multi-rate configuration control 0|0 = STS-48 / STM-16 Mode 0|1 = STS-3 / STM-1 Mode 1|0 = STS-12 / STM4 Mode 1|1 = Invalid
2. FRD0
Allows manual control of framing behavior. FRD0 state controls whether the device is actively searching for a frame boundary. Manual control will only function if FRD1 is set to a `1'. 0 = Do not perform frame boundary acquisition 1 = Attempt frame boundary acquisition Determines whether reframing is automatically performed or controlled by the setting of the FRD0 register. Automatic reframing uses the status of the SEF output to determine whether reframing needs to take place, forcing frame acquisition as long as SEF is detected. 0 = Frame acquisition is performed upon detection of SEF 1 = Frame Acquisition is controlled manually Controls detection width of A1/A2 boundary 0|0 = Search for 12 bit pattern: h'F62 0|1 = Search for 48 bit pattern: h'F6F6F6282828 1|0 = Search for 24 bit pattern: h'F6F628 1|1 = Do not search for start of frame. AIS Insertion mode 0 1 =
3. FRD1
4. SL1 | SL0
5. AIS
= =
Retransmit received data Replace received data with internally generated AIS
6. B2G
In AIS mode if this bit is set to a "1", B2 calculation on #1 STS-1 frame is performed. If this bit is set to "0", the B2 field of the #1 STS-1 AIS frame is set to 8'hFF. Disable 16-bit PECL output bus RXPOUT[15:0]. The user should leave these outputs un-terminated to reduce power consumption and noise if they are disabled. 0 = Enable RXPOUT[15:0] 1 = Disable RXPOUT[15:0]. Pass Through Mode. 0 1
7. DP
8. PT
= =
Normal Operation Disable modification of overhead bytes & BIP recalculation
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9. DD Disable descrambling 0 = 1 = Disable scrambling 0 1
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Normal Operation Disable descrambling of incoming data
10. DS
= =
Normal Operation Disable scrambling of outgoing data
11. NS
Non-SONET: Allows device to pass non-SONET data such as Gigabit Ethernet. NOTE: If non-SONET data is being transmitted, Frame Detect must be disabled. (When NS="1", set FRD1="1" and FRD0="0"). 0 = SONET data transmitted 1 = non-SONET data transmitted Forced write of A1/A2 boundary. FWAx = "1" forces all A1 and A2 to be re-written (as described in the A1/A2 boundary refresh section) 0 = Normal Operation 1 = Forced re-write of A1/A2
12. FWAx
13. MXC[1:0] VSC8151 CMU reference generator output clock selection (see Figure 3)
MXC1
0 0 1 1
MXC0
0 1 0 1
CKREFP/N, CKREFT Reference Generator Outputs
CMU Ref Gen Outputs = Referenced from RXSCLKIN/32 (Transport Mode) CMU Ref Gen Outputs = Referenced from external 77MHz PECL AIS Refclk (I_RCAIS) CMU Ref Gen Outputs = Referenced from external 155MHz PECL AIS Refclk (I_RCAIS ) CMU Ref Gen Outputs = Based off external TTL AIS Refclk (I_RCVCO) 77MHz
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2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
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AC Timing Characteristics
Figure 8: Overhead Output Timing Diagram
RXOHOUT[7:0]
E2
A1 TOHSU
A2 TOHH
C1/J0
RXOHCLK
TOHCLKW
RXFPOUT
TFPSU TFPW
Table 3: Overhead Output Timing (STS-48/STM-16 Mode) Parameter
TOHSU TOHH TOHCLKW TFPSU TFPW
Description
Overhead output setup time with respect to RXOHCLK Overhead output hold time with respect to RXOHCLK Overhead output clock period Frame pulse setup time with respect to RXOHCLK Frame pulse width
Min
70.5 70.5 -- 88 51.34
Typ
-- -- 154 -- --
Max
-- -- -- -- 51.44
Units
ns ns ns ns ns
Note: Generated Waveforms are synchronous and assume a 2.488GHz RXSCLKIN signal.
Table 4: Overhead Output Timing (STS-12/STM-4 Mode) Parameter
TOHSU TOHH TOHCLKW TFPSU TFPW
Description
Overhead output setup time with respect to RXOHCLK Overhead output hold time with respect to RXOHCLK Overhead output clock period Frame pulse setup time with respect to RXOHCLK Frame pulse width
Min
73.5 73.5 -- 104 51.34
Typ
-- -- 154 -- --
Max
-- -- -- -- 51.44
Units
ns ns ns ns ns
Note: Generated Waveforms are synchronous and assume a 622MHz RXSCLKIN signal.
Table 5: Overhead Output Timing (STS-3/STM-1 Mode) Parameter
TOHSU TOHH TOHCLKW TFPSU TFPW
Description
Overhead output setup time with respect to RXOHCLK Overhead output hold time with respect to RXOHCLK Overhead output clock period Frame pulse setup time with respect to RXOHCLK Frame pulse width
Min
102 102 -- 155 51.34
Typ
-- -- 154 -- --
Max
-- -- -- -- 51.44
Units
ns ns ns ns ns
Note: Generated Waveforms are synchronous and assume a 155MHz RXSCLKIN signal. (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
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2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Figure 9: Framing and B1 Error Output Timing
TFPW
RXFPOUT
TFERRPW
RXFRERR
TFERRSU TSEFSU
RXSEF
Note: Waveforms not to scale
Table 6: Framing and B1 Error Output Timing (STS-48/STM-16 Mode) Parameter
TFPW TFERRSU TFERRPW TSEFSU Frame Pulse Width Frame Boundary Error delay with respect to RXFPOUT Frame Boundary Error pulse width high SEF transition delay time with respect to RXFPOUT
Description
Min
-- -- -- --
Typ
51.4 61.2 25.7 48.3
Max
-- -- -- --
Units
ns ns ns ns
Note: Generated Waveforms are synchronous and assume a 2.488GHz RXSCLKIN signal.
Table 7: Framing and B1 Error Output Timing (STS-12/STM-4 Mode) Parameter
TFPW TFERRSU TFERRPW TSEFSU Frame Pulse Width Frame Boundary Error delay with respect to RXFPOUT Frame Boundary Error pulse width high SEF transition delay time with respect to RXFPOUT
Description
Min
-- -- -- --
Typ
51.4 64.4 51.4 51.4
Max
-- -- -- --
Units
ns ns ns ns
Note: Generated Waveforms are synchronous and assume a 622MHz RXSCLKIN signal.
Table 8: Framing and B1 Error Output Timing (STS-3/STM-1 Mode) Parameter
TFPW TFERRSU TFERRPW TSEFSU Frame Pulse Width Frame Boundary Error delay with respect to RXFPOUT Frame Boundary Error pulse width high SEF transition delay time with respect to RXFPOUT
Description
Min
-- -- -- --
Typ
51.4 0 51.4 103
Max
-- -- -- --
Units
ns ns ns ns
Note: Generated Waveforms are synchronous and assume a 155MHz RXSCLKIN signal.
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Figure 10: Transmit Frame Pulse Timing Diagram
Transmitted Frame bytes
E2
E2
E2
Payload bytes of Row 9
TXFPOUT TB TFPW
Table 9: Transmit Frame Pulse Timing Parameter
TFPW TB (OC-48) TB(OC-12) TB(OC-3)
Description
Transmit Frame Pulse Width Transmitted Byte Cycle Time Transmitted Byte Cycle Time Transmitted Byte Cycle Time
Min
-- -- -- --
Typ
51.2 3.2 12.8 51.2
Max
-- -- -- --
Units
ns ns ns ns
Figure 11: On Chip Register File Access Port Timing Diagram
TXADDR[5:0]
TXOHDATA[7:0] TXOHWI
TXWRENA
TSU TWE
TH TCYC
Table 10: On Chip Register File Access Port Timing Parameter
TSU TH TWE TCYC
Description
Setup time for data/address Hold time for data/address Write enable low Write cycle time
Min
50 50 50 375
Typ
-- -- -- --
Max
-- -- -- --
Units
ns ns ns ns
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2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Figure 12: Serial Data Input Timing Diagram
TRXSCLKIN RXSCLKINRXSCLKIN+ TRXSSU TRXSH RXSIN+ RXSIN-
Table 11: Serial Data Input Timing Parameter
TRXSCLKIN TRXSSU TRXSH
Description
Serial Receive clock period Serial Receive input data RXSIN setup time with respect to falling edge of RXSCLKIN+ Serial Receive input data RXSIN hold time with respect to falling edge of RXSCLKIN+
Min
401.9 100 75
Typ
-- -- --
Max
-- -- --
Units
ps ps ps
Figure 13: Parallel Data Input Timing Diagram
TPOUTCLK POUTCLK TRXPSU RXPIN[15:0] TRXPH
Table 12: Parallel Data Input Timing Parameter
TPOUTCLK TRXPSU TRXPH
Description
Parallel output clock period Parallel receive input data RXPIN setup time with respect to falling edge of POUTCLK output Parallel receive input data RXPIN hold time with respect to falling edge of POUTCLK output
Min
103.2 2.4 1.0
Typ
-- -- --
Max
6.45 -- --
Units
ns ns ns
Note: Parallel output clock is synchronously generated 50/50 1/16th the frequency of the serial clock input (RXSCLKIN)
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Figure 14: Serial Data Output Timing Diagram
TTXSCLKIN TXSCLKIN+ TXSCLKINTTXSOUT TXSOUT+ TXSOUT-
Table 13: Serial Data Output Timing Parameter
TTXSCLKIN TTXSOUT
Description
Serial Receive clock period Propagation delay from rising edge of TXSCLKIN+/- to output edge of TXSOUT+/-
Min
401.9 430
Typ
-- --
Max
-- 630
Units
ps ps
Figure 15: Serial Data Output Timing Skew
TTXSCLKOUT TXSCLKOUT+ -TSKW TXSOUT+ TXSOUT+TSKW
Table 14: Serial Data Output Skew Parameter
TTXSCLKOUT TTSKW
Description
Serial transmit clock period Propagation delay from falling edge of TXSCLKOUT+ to output edge of TXSOUT+/-
Min
401.9 --
Typ
-- --
Max
-- 100
Units
ps ps
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2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Figure 16: Parallel Data Output Timing Diagram
TPOUTCLK POUTCLK TP TP
TXPOUT[15:0]
Table 15: Parallel Data Output Timing Parameter
TPOUTCLK TP
Description
Parallel output clock period Propagation delay from falling edge of POUTCLK to output edge of TXPOUT[15:0]
Min
103.2 -500
Typ
-- --
Max
6.45 500
Units
ns ps
Note: Parallel output clock is synchronously generated 50/50 1/16th the frequency of the serial clock input (RXSCLKIN)
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DC Characteristics
Table 16: High-Speed Differential Inputs and Outputs (HSPECL) Parameter Description
Data Output differential voltage (Peak to Peak, Single-ended) Clock Output differential voltage (Peak to Peak, Single-ended) Output common-mode voltage Output Impedance Input differential voltage
Min
550
Typ
--
Max
1200
Units
mV
Conditions
Load = 100 Ohms across TXSOUT+/- at load Load = 100 Ohms across TXCLKOUT+/- at load Load = 100 Ohms across diff pair Guaranteed, not tested. AC Coupled, internally biased to VTTL/2
VODATA VOCLK VOCM RO VID
450 2100 40 450
-- -- -- --
1200 3000 60 --
mV mV ohms mV
Table 17: Low-Speed Parallel LVPECL Inputs and Outputs Parameter Description
Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current
Min
VTTL-1020 VTTL-2000 VTTL-1165 VTTL-2000 -- -50
Typ
-- -- -- -- -- --
Max
VTTL-700 VTTL-1620 VTTL-700 VTTL-1475 200 --
Units
mV mV mV mV A A -- -- -- --
Conditions
VOH VOL VIH VIL
IIH IIL
VIN = VIH (max) VIN = VIL (min)
Note: (1) External Reference (VREF) = VTTL -1.32V 25mV. (2) Load = 50 to VTTL -2.0V. (3) External VREF current is 50A per Input.
Table 18: TTL Inputs and Outputs Parameter Description
Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current
Min
2.4 0 2.0 0 -50
Typ
-- -- -- -- -- --
Max
-- 0.4 VTTL + 1.0V 0.8 500 --
Units
V V V V A A
Conditions
IOH = -8mA IOL = 8mA -- -- VIN = 2.4V VIN = 0.4V
VOH VOL VIH VIL
IIH IIL
Table 19: Power Supply Currents (+2V/+3.3V Supplies, Outputs Open) Parameter
ITTL IMM PD
Description
Power supply current from VTTL Power supply current from VMM Power dissipation
(Max)
380 1100 3.6
Units
mA mA W
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Absolute Maximum Ratings
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Power Supply Voltage (VCC) Potential to GND ............................................................................-0.5 V to +4.3 V Power Supply Voltage (VMM) Potential to GND ...........................................................................-0.5 V to +3.0 V TTL Input Voltage Applied ..........................................................................................................-0.5 V to + 5.5V ECL Input Voltage Applied ...................................................................................................+0.5 V to VTT -0.5 V Output Current (IOUT) ................................................................................................................................... 50 mA Case Temperature Under Bias (TC) ................................................................................................-55o to + 125oC Storage Temperature (TSTG) ...........................................................................................................-65o to + 150oC
Note: Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
Recommended Operating Conditions
Power Supply Voltages (VCC)...............................................................................................................+3.3V 5 % Power Supply Voltages (VMM)..............................................................................................................+2.0V 5 % Commercial Operating Temperature Range* (T).................................................................................. 0o to 85oC
Notes: (1)Lower limit of specification is ambient temperature and upper limit is case temperature. (2)Customer must use air cooled/heatsink environment to meet thermal requirements of the package. (3)Suggested power up of 8151 is +2.0V supply first, then +3.3V supply.
ESD Ratings
Proper ESD procedures should be used when handling this product. The VSC8151 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V.
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Package Pin Descriptions
Table 20: Pin Identification Signal
VREF VCC VEE VMM NC CKREFP CKREFN VTERM (RXSCLKIN) VCC VCC VEE VEE VCC TXSOUT VCC TXSOUT + DOPWR VCC TXSCLKOUTTXSCLKOUT+ VCC CLKOPWR VCC RXSCLKIN + RXSCLKIN VEE TXSCLKINTXSCLKIN+ RXSIN + RXSIN VTERM (TXSCLKIN) VTERM (RXSIN)
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
I/O
PWR PWR PWR PWR -- PWR PWR PWR PWR PWR O PWR O PWR PWR PWR I I PWR -- -- I I
Level
+1.98V +3.3V GND +2.0V -- PECL PECL 0 -> 3.3V +3.3V +3.3V GND GND +3.3V HSECL +3.3V HSECL GND / +3.3V +3.3V HSECL HSECL +3.3V GND / +3.3V +3.3V HSECL HSECL GND -- -- HSECL HSECL 0 -> 3.3V 0 -> 3.3V Leave Unconnected
Pin Description
PECL Input reference. No connect if RXPIN[15:0] is not used.
Output Clock for external AIS CMU (true) Output Clock for external AIS CMU (complement) High Speed Clock Input Termination Voltage (Demux)
Serial Data Output, complement 2.5Gb/s PECL Output Driver Supply Pin Serial Data Output, true Serial data output power down (tie to VCC to power down, GND otherwise) 2.5Gb/s PECL Output Driver Supply Pin Serial Clock Output, complement Serial Clock Output, true Serial clock output power down (tie to VCC to power down, GND otherwise) 2.5Gb/s PECL Output Driver Supply Pin Serial Clock Input for Demux, true Serial Clock Input For Demux, complement Serial Clock Input for Mux, complement Serial Clock Input for Mux, true Serial Data Input, true Serial Data Input, complement High Speed Clock Input Termination Voltage (for Mux) High Speed Data Input Termination Voltage
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Table 20: Pin Identification Signal
NC NC NC NC VMM VEE VCC EQULOOP NC NC RXPIN15 RXPIN14 RXPIN13 RXPIN12 RXPIN11 RXPIN10 VCC VMM RXPIN9 RXPIN8 VEE RXPIN7 RXPIN6 VMM RXPIN5 RXPIN4 VMM RXPIN3 RXPIN2 VCC RXPIN1 RXPIN0 VMM NC RXFPOUT VEE SEF RXOHCLK
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Pin
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
I/O
-- -- -- -- PWR PWR PWR I -- -- I I I I I I PWR PWR I I PWR I I PWR I I PWR I I PWR I I PWR -- O PWR O O
Level
-- -- -- -- +2.0V GND +3.3V TTL -- -- PECL PECL PECL PECL PECL PECL +3.3V +2.0V PECL PECL GND PECL PECL +2.0V PECL PECL +2.0V PECL PECL +3.3V PECL PECL +2.0V -- TTL GND TTL TTL Leave Unconnected 16 bit PECL input bus 16 bit PECL input bus 16 bit PECL input bus 16 bit PECL input bus 16 bit PECL input bus 16 bit PECL input bus 16 bit PECL input bus 16 bit PECL input bus 16 bit PECL input bus 16 bit PECL input bus Leave Unconnected Leave Unconnected Leave Unconnected Leave Unconnected
Pin Description
RXPIN[15:0] parallel bus input enable. Tie low to use serial input Leave Unconnected Leave Unconnected 16 bit PECL input bus 16 bit PECL input bus 16 bit PECL input bus 16 bit PECL input bus 16 bit PECL input bus 16 bit PECL input bus
Received Frame Pointer (Pulse High) Severely Errored Frame Indicator (Active High) Receive Overhead Output Clock
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2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Table 20: Pin Identification Signal
VEE VCC I_RCVCO NC I_RCAIS NC NC NC NC NC LOS VCC VEE VMM VCC VEE RXFRERR TXFPOUT RXOHOUT4 RXOHOUT5 RXOHOUT6 RXOHOUT7 RXOHOUT0 RXOHOUT1 VEE RXOHOUT2 RXOHOUT3 VCC LOF CKREFT NC TXPOUT15 VCC TXPOUT14 TXPOUT13 VCC TXPOUT12 NC
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Pin Description
Pin
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
I/O
PWR PWR -- -- -- -- -- -- I PWR PWR PWR PWR PWR O O O O O O O O PWR O O PWR O O -- O PWR O O PWR O --
Level
GND +3.3V TTL -- PECL -- -- -- -- -- TTL +3.3V GND +2.0V +3.3V GND TTL TTL TTL TTL TTL TTL TTL TTL GND TTL TTL +3.3V TTL TTL -- PECL +3.3V PECL PECL +3.3V PECL -- 16 bit PECL output bus Leave Unconnected 16 bit PECL output bus 16 bit PECL output bus Loss of Frame Received Overhead Bus Received Overhead Bus Received Frame Error Transmit Frame Pointer Received Overhead Bus Received Overhead Bus Received Overhead Bus Received Overhead Bus Received Overhead Bus Received Overhead Bus
TTL Reference Input (Set with MXC[1:0]) (77MHz) Leave Unconnected PECL Reference Input (Set with MXC[1:0]) Leave Unconnected Leave Unconnected Leave Unconnected Leave Unconnected Leave Unconnected Loss of Signal
Output Clock for external AIS CMU (Set with MXC[1:0]) Leave Unconnected 16 bit PECL output bus
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Table 20: Pin Identification Signal
TXADDR0 TXADDR1 TXADDR2 TXADDR3 TXWRENA TXADDR4 VMM VCC VMM VEE VCC TXOHWI TXOHIN7 TXOHIN6 TXOHIN5 TXOHIN4 TXOHIN3 TXOHIN2 TXOHIN1 TXOHIN0 VCC VCC TXPOUT11 TXPOUT10 VEE TXPOUT9 TXPOUT8 VMM TXPOUT7 TXPOUT6 VCC TXPOUT5 TXPOUT4 VCC TXPOUT3 TXPOUT2 VMM TXPOUT1
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Pin
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146
I/O
I I I I I I PWR PWR PWR PWR PWR I I I I I I I I I PWR PWR O O PWR O O PWR O O PWR O O PWR O O PWR O
Level
TTL TTL TTL TTL TTL TTL +2.0V +3.3V +2.0V GND +3.3V TTL TTL TTL TTL TTL TTL TTL TTL TTL +3.3V +3.3V PECL PECL GND PECL PECL +2.0V PECL PECL +3.3V PECL PECL +3.3V PECL PECL +2.0V PECL 16 bit PECL output bus 16 bit PECL output bus 16 bit PECL output bus 16 bit PECL output bus 16 bit PECL output bus 16 bit PECL output bus 16 bit PECL output bus 16 bit PECL output bus 16 bit PECL output bus 16 bit PECL output bus 16 bit PECL output bus TX Regfile Write Inhibit TX Regfile Data Input TX Regfile Data Input TX Regfile Data Input TX Regfile Data Input TX Regfile Data Input TX Regfile Data Input TX Regfile Data Input TX Regfile Data Input TX Regfile Address TX Regfile Address TX Regfile Address TX Regfile Address TX Regfile Write Enable TX Regfile Address Input
Pin Description
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Table 20: Pin Identification Signal
TXPOUT0 VEE POUTCLK NC VCC VCC NC NC TEST TEST NC SYSRST NC TEST
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VSC8151
Pin Description
16 bit PECL output bus 16 bit PECL bus clock Leave Unconnected
Pin
147 148 149 150 151 152 153 154 155 156 157 158 159 160
I/O
O PWR O -- PWR PWR -- -- I I -- I -- I
Level
PECL GND PECL -- +3.3V +3.3V -- -- GND GND -- TTL -- GND Leave Unconnected Leave Unconnected Test Input (TTL CLK) Test Input (TTL SEL) Leave Unconnected System Reset Leave Unconnected Test Input
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Package Information
EXPOSED HEATSINK 20.32 +/- .50 DIA. Pin 160 Pin 1
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
HEATSINK INSTRUSION
Key
A A1 A2
E1 E
mm
4.10 0.25 3.49 31.20 28,00 31.20 28.00 0.88 0.65 0.30 0-7 .30 .20
Tolerance
MAX MIN 0.10 0.20 0.10 0.20 0.10 +.15/-.10 BASIC 0.05 TYP TYP
D D1 E E1 L e b R R1
D1 D
10 TYP.
Notes: (1) Drawing not to scale Package #101-285-5, Issue #1
A
A2
e
10 TYP.
R
.
A1 A STANDOFF
R1
.
0.17 MAX. 0.25 L
q b
LEAD COPLANARITY
Notes: 1) 2) 3)
160 Plastic Quad Flat Pack
Drawing is not to scale All dimensions in mm Package represented is also used for the 144, 184, & 208 PQFP packages. Pin count drawn does not reflect the 160 package.
G52225-0, Rev. 2.9 12/1/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 27
VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Advance Product Information
VSC8151
Package Thermal Characteristics
The VSC8151 is packaged in an 160 pin, 28mm x 28mm thermally enhanced PQFP (EDQUAD) with an exposed heatsink. These packages use industry-standard JDEC footprints, but have been enhanced to improve thermal dissipation. The construction of the packages are as shown in Figure 13. A heat sink may be necessary depending on the ambient temperature and airflow available in your system. Commercially available heatsinks are available to improve ca so that the case temperature is kept within the 85C specification.
Figure 17: Package Cross Section
Exposed Heat Slug Insulator
Plastic Molding
Lead
Wire Bond
Die
Table 21: 160-Pin Enhanced PQFP Thermal Resistance Symbol
ca-0 ca-1 ca-2 ca-4
Description
Thermal resistance from case to ambient, still air Thermal resistance from case to ambient, 1 m/sec air Thermal resistance from case to ambient, 2 m/sec air Thermal resistance from case to ambient, 3 m/sec air
Value
24 14 11 10
Units
oC/W oC/W oC/W oC/W
Page 28
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52225-0, Rev. 2.9 12/1/99
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8151
Ordering Information
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
The order number for this product is formed by a combination of the device number, and package type.
VSC8151
Device Type VSC8151: 2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
QV
Package QV: 160PQFP, 28mm Body
Notice
This document contains information about a new product during its early sampling phase. The information in this document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to design or order placement.
Warning
Vitesse Semiconductor Corporation's products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited.
G52225-0, Rev. 2.9 12/1/99
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 29
VITESSE
SEMICONDUCTOR CORPORATION
2.488Gb/s SONET/SDH STS-48/STM-16 Section Terminator
Advance Product Information
VSC8151
Page 30
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52225-0, Rev. 2.9 12/1/99

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